Welcome to the Young Architect Workshop!

A Workshop for Early-stage Graduate Students in Computer Architecture

Panel Discussion: Demystifying Grad School

Panelist: Esha Choukse (Microsoft Azure Research)

Bio: Esha Choukse is currently a Principal Researcher at Microsoft in the Azure Research - Systems group in Redmond, WA. Her research focuses on efficient and sustainable AI deployment across the stack, crossing the layers of AI platform, hardware, and datacenter infrastructure, and has been published at premier venues like ISCA, ASPLOS, MICRO, and HPCA. Choukse received her PhD in Computer Architecture from the University of Texas at Austin. Contact her at esha.choukse@microsoft.com.

Panelist: Boris Grot (University of Edinburgh and Huawei Research)

Bio: Boris Grot is a Professor in the School of Informatics at the University of Edinburgh, where he leads the Edinburgh Architecture and Systems Lab (EASE Lab). His research interests include server hardware and software stacks, networking, and datacenter-scale computing. Boris is a member of the MICRO and HPCA Halls of Fame and a recipient of multiple awards for his research. He is on the executive committee of ACM SIGARCH, through which he has been involved in a number of community-focused initiatives, including an ongoing one to involve more PhD students in the conference peer-reviewing process.

Panelist: Christos Kozyrakis (Stanford University and NVIDIA)

Bio: Christos Kozyrakis is a professor of EE & CS at Stanford University and a computer architecture researcher at Nvidia. He is currently working on cloud computing technology, systems for AI, and AI for systems. He is a fellow of the ACM and the IEEE. He has received the ACM SIGARCH Maurice Wilkes Award, the ISCA Influential Paper Award, the ASPLOS Influential Paper Award, the NSF Career Award, the Okawa Foundation Research Grant, and faculty awards by IBM, Microsoft, and Google.

Panelist: Nandita Vijaykumar (University of Toronto)

Bio: Nandita Vijaykumar is an Assistant Professor at the Department of Computer Science at the University of Toronto. She leads the embARC research group at the University of Toronto. She is also affiliated with the Vector Institute for Artificial Intelligence. She received her Ph.D. from Carnegie Mellon University. She has previously worked for AMD, Intel, Microsoft, and Nvidia.

Her research interests lie at the intersection of computer architecture/compilers/systems, and computer vision/robotics/ML. Her group’s research has been supported by many organizations and corporations including Intel, AMD, Nvidia, Sony, Sapeon, NSERC, MITACS, CentML, and CSE Canada. She is the recipient of the Connaught New Researcher Award, the Benjamin Garver Lamme Fellowship, is a Qualcomm Fellowship Finalist, and was inducted into the ISCA Hall of Fame.

Panelist: John Wickerson (Imperial College London)

Bio: John Wickerson is a Senior Lecturer (roughly equivalent to an Associate Professor in the US) in the Department of Electrical and Electrical Engineering at Imperial College London. Before that, he was a postdoc and an Imperial College Research Fellow in the same department; before that, he was a postdoc in the Department of Computing at Imperial College London; and before _that_, he did his BA and PhD in Computer Science at the University of Cambridge.

His main research topic at the moment is making EDA tools (logic synthesis, high-level synthesis, equivalence checkers, etc.) more reliable through the use of formal verification (PLDI 2024) and better testing (DVCon 2024). Some other current or recent research topics include: proving that the CXL protocol guarantees cache coherence (ASPLOS 2025), fuzzing quantum compilers (PLanQC 2025), testing concurrency support in C compilers (OOPSLA 2024), and improving the semantics of GPU programming languages (POPL 2023).

At Imperial he teaches Compilers to second-years and Verification to fourth-years, and he also serves as the course director of the Electrical and Information Engineering degree. And when he's not doing any of these things, he enjoys writing new programming-oriented lyrics to old songs.

Accepted Papers:

• System-level Analysis and Integrated Acceleration for Real-time and Efficient Embodied AI Systems
  Yuhang Du (University of Minnesota), Yang (Katie) Zhao (University of Minnesota), Zishen Wan (Georgia Tech)
• I2P: Incorrect-Path Prediction
  Naomi Rehman (UC Santa Cruz), Surim Oh (UC Santa Cruz), Heiner Litz (UC Santa Cruz)
• A Language for Microarchitectural Security Evaluation
  Guokai Chen (EPFL), Thomas Bourgeat (EPFL)
• DRAMselfly: Fault-Tolerant DRAM for Machine Learning at Scale
  Aster Plotnik (University of Toronto), Natalie Enright Jerger (University of Toronto), Mark Jeffrey (University of Toronto)
• Hermes' SERenaDE: Hardware Acceleration of Serialization Frameworks
  Christos Zarkos (MIT), Nikita Lazarev (MIT), Shabnam Sheikhha (MIT), Christina Delimitrou (MIT)
• Adaptive Caching and Scheduling for Many-Adapter LLM Inference Environments
  Nikoleta Iliakopoulou (University of Illinois at Urbana-Champaign), Jovan Stojkovic (University of Illinois at Urbana-Champaign), Chloe Alverti (University of Illinois at Urbana-Champaign), Tianyin Xu (University of Illinois Urbana-Champaign), Hubertus Franke (IBM Research), Josep Torrellas (University of Illinois at Urbana-Champaign)
• Rethinking IOMMU for Future IO Devices
  Madhur Kumar (EPFL), Yuanlong Li (EPFL), Yoav Etsion (Technion), Abhishek Bhattacharjee (Yale University), Arkaprava Basu (Indian institute of Science), Babak Falsafi (EPFL), Sanidhya Kashyap (EPFL), Mathias Payer (EPFL)
• Harmony: Co-Optimizing Parallelism and Locality to Bound Performance
  Jennifer Brana (Carnegie Mellon University), Nathan Beckmann (Carnegie Mellon University)
• TimeSafe: Isolated Time-Based Defenses for Storage Systems
  Jonah Rosenblum (University of Michigan), Juechu Dong (University of Michigan), Peter Chen (University of Michigan), Satish Narayanasamy (University of Michigan)
• Going From Gates To Cycles: Fine-Grained Instruction Scheduling For Enhanced Concurrency In Neutral Atom Quantum Computers
  Won Joon Yun (University of Texas at Austin), Poulami Das (University of Texas at Austin)
• A Methodology for Extending Open-Source Trusted Execution Environments within Architectural Simulators
  Will Buziak (Colorado School of Mines), Samuel Thomas (Brown University), Iris Bahar (Colorado School of Mines), Tamara Lehman (University of Colorado)
• Weightless Language Models: Towards Ultra Low-Energy Edge-Efficient LLMs
  Shashank Nag (The University of Texas at Austin), Lizy John (The University of Texas at Austin)
• GainSight: Profile-Guided Design for Heterogeneous On-Chip Memories in Next-Generation AI Accelerators
  Peijing Li (Stanford University), Thierry Tambe (Stanford University)
• Unified Frontend Prefetching
  Mária Ďuračková (University of Edinburgh)

SUBMIT

Eligibility

Applicants must be either (a) research-active undergraduate students aiming for graduate school, or (b) graduate students (Masters and/or PhD) in computer architecture and related fields who have completed less than 3 years of graduate school at the time of the workshop. A note from the student’s research advisor attesting this is required as part of the submission.

Eligible students are invited to submit their early stage or on-going work to this workshop. Submitted work should not have been presented as part of a prior ACM/IEEE conference.

Note: This workshop is not a venue for publication and there will be no formal proceedings.

Topics of Interest

The workshop invites papers from all areas of computer architecture, broadly defined. Topics of interest include, but not limited to:

• Datacenter systems
• Hardware acceleration
• Memory hierarchy
• Virtualization
• Security
• Microarchitecture
• GPUs
• Parallel architectures
• Emerging technologies

Submission Guidelines

The goal of this workshop is to help students think about a problem/idea in an holistic manner and communicate your ideas to the wider community, so that we can provide some valuable early-stage feedback. To this end, we encourage you to cover the following aspects in your submission:

• Scope of problem/idea: Provide clear context for and scope of the problem(s) or idea(s) you intend to work on. This will likely form the basis of the introduction/background sections of your future work(s).
• Solution: Provide an overview of the design and implementation aspects of your solution(s) to the problem(s) described above. Given this is on-going work, focus more on providing breadth than depth. For example, beside describing the design of your idea, enlist the various system aspects which your proposed solutions will affect (e.g. does your proposed solution affect coherence protocols?) and that if you plan to discuss these effects in your future submission(s).
• Evaluation methodology: Discuss the evaluation methodology you plan to adopt to test the efficacy of your ideas. For example, the workloads that you plan to use, the tools you’ll employ (e.g., architectural simulator, real world experiments, FPGA prototypes), etc.
• Related work: This can be the traditional related work section. Please specify if you plan to quantitatively compare against some prior work.

Submission Details

• Submissions must be PDF files, in 2-column, single-spaced, 10pt format, at most 2 pages long, not including references.
• Submissions are double-blind. Please do not have any author identifying information in the paper submitted.
• Please have your research advisor send the workshop organizers an email with the following subject line “<Your name> meets YArch’24 eligibility requirements” to youngarchitectw@gmail.com.
• Submission site: https://yarch2025.hotcrp.com
• Registration deadline: January 10, 2025
• Submission deadline: January 17, 2025, 18:00pm EST

Declaring Conflicts

When registering a submission, all its co-authors must provide information about conflicts with the YArch'25 program committee members. You are conflicted with a member if:

1. you are currently employed at the same institution, have been previously employed at the same institution within the past two years, or are going to begin employment at the same institution;
2. you have a past or present association as thesis advisor or advisee (no time limit);
3. you have collaborated on a project, publication, grant proposal, or editorship within the past two years;
4. or, you have spouse or first-degree relative relations.

Funding FAQ

1. We aim to fund one person per paper (the presenter/first author).
2. Depending on available funding we may only cover partial costs.
3. We aim to fund the presenters from all accepted papers.

Sponsors: